Pyverilog

Pyverilog is a Python-based Hardware Design Processing Toolkit for Verilog HDL, providing a parser, dataflow analyzer, controlflow analyzer, and code generator. It allows users to parse Verilog code into an Abstract Syntax Tree (AST), analyze its structure, and extract design information. The current version is 1.3.0, and releases occur periodically, typically every few months, addressing bugs and adding new features.