{"library":"pyverilog","title":"Pyverilog","description":"Pyverilog is a Python-based Hardware Design Processing Toolkit for Verilog HDL, providing a parser, dataflow analyzer, controlflow analyzer, and code generator. It allows users to parse Verilog code into an Abstract Syntax Tree (AST), analyze its structure, and extract design information. The current version is 1.3.0, and releases occur periodically, typically every few months, addressing bugs and adding new features.","language":"python","status":"active","last_verified":"Fri Apr 17","install":{"commands":["pip install pyverilog ply"],"cli":{"name":"pyverilog","version":"sh: 1: pyverilog: not found"}},"imports":["from pyverilog.vparser.parser import VerilogParser","import pyverilog.vparser.ast as vast","from pyverilog.dataflow.dataflow import DataflowAnalyzer","from pyverilog.dataflow.graph import DotGraph"],"auth":{"required":false,"env_vars":[]},"quickstart":{"code":"import os\nfrom pyverilog.vparser.parser import VerilogParser\nimport pyverilog.vparser.ast as vast\nfrom pyverilog.dataflow.dataflow import DataflowAnalyzer\nfrom pyverilog.dataflow.graph import DotGraph\n\n# Create a dummy Verilog file for parsing\nverilog_code = \"\"\"\nmodule test_module (input clk, input rst, output reg [7:0] count);\n  always @(posedge clk or posedge rst) begin\n    if (rst) begin\n      count <= 8'h00;\n    end else begin\n      count <= count + 1;\n    end\n  end\nendmodule\n\"\"\"\n\nwith open('example.v', 'w') as f:\n    f.write(verilog_code)\n\n# 1. Parse the Verilog file into an AST\nparser = VerilogParser()\nast = parser.parse(['example.v'])\n\nprint(\"--- Verilog AST --- \")\n# ast.show() # Uncomment to print the full AST\n\n# 2. Perform Dataflow Analysis\nanalyzer = DataflowAnalyzer()\nanalyzer.visit(ast)\n\n# Get dataflow graph and print some nodes\ndfg = analyzer.get_dfg()\nprint(\"\\n--- Dataflow Analysis (some nodes) ---\")\nfor node_id, node in dfg.items():\n    if isinstance(node_id, vast.Port) or isinstance(node_id, vast.Reg):\n        print(f\"Node: {node_id.name}, Type: {type(node_id).__name__}, Defs: {len(node.definitions)}\")\n\n# 3. Generate a DOT graph (requires graphviz and dot command)\n# try:\n#     graph = DotGraph(dfg)\n#     graph.write_dot('dfg.dot')\n#     print(\"\\nDataflow graph written to dfg.dot (requires Graphviz to visualize).\")\n# except Exception as e:\n#     print(f\"\\nCould not generate DOT graph: {e} (Is Graphviz installed?)\")\n\n# Clean up the dummy file\nos.remove('example.v')\n","lang":"python","description":"This quickstart demonstrates how to parse a simple Verilog module into an Abstract Syntax Tree (AST) using `VerilogParser`, and then perform a basic dataflow analysis using `DataflowAnalyzer`. It prints key nodes from the AST and basic information from the dataflow graph. To visualize the dataflow graph as an image, you would also need to install Graphviz and use `DotGraph` to write a '.dot' file which can then be rendered externally.","tag":null,"tag_description":null,"last_tested":null,"results":[]},"compatibility":null}