PeakRDL-regblock
JSON →PeakRDL-regblock is a free and open-source control & status register (CSR) compiler. It translates SystemRDL register descriptions into synthesizable SystemVerilog RTL modules for hardware designs. The library is actively maintained, with a recent major release (1.0.0) in April 2025, and subsequent minor releases, currently at version 1.3.1, indicating a rapid release cadence.
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Resources
API endpoints
full doc /v1/registry/peakrdl-regblock
compatibility /v1/registry/peakrdl-regblock/compatibility