{"library":"peakrdl-regblock","type":"library","category":null,"description":"PeakRDL-regblock is a free and open-source control & status register (CSR) compiler. It translates SystemRDL register descriptions into synthesizable SystemVerilog RTL modules for hardware designs. The library is actively maintained, with a recent major release (1.0.0) in April 2025, and subsequent minor releases, currently at version 1.3.1, indicating a rapid release cadence.","language":"python","status":"active","version":"1.3.1","tags":["SystemRDL","SystemVerilog","RTL","FPGA","ASIC","CSR","compiler","hardware design","register automation"],"install":[{"cmd":"pip install peakrdl-regblock","imports":["from peakrdl_regblock import RegblockExporter","from systemrdl import RDLCompiler"]},{"cmd":"pip install peakrdl-regblock[cli]","imports":[]}],"homepage":null,"github":"https://github.com/SystemRDL/PeakRDL-regblock","docs":"https://peakrdl-regblock.readthedocs.io/","changelog":"https://github.com/SystemRDL/PeakRDL-regblock/releases","pypi":"https://pypi.org/project/peakrdl-regblock/","npm":null,"openapi_spec":null,"status_page":null,"smithery":null,"compatibility":{"summary":{"python_range":"3.10–3.9","success_rate":100,"avg_install_s":2.8,"avg_import_s":0.36,"wheel_type":"wheel"},"url":"https://checklist.day/v1/registry/peakrdl-regblock/compatibility"},"provenance":{"verified_status":"passing","verified_at":"Sun Jun 28","last_verified":"Sun Jun 28","next_check":"Tue Jul 28","install_tag":null}}