mcp4eda
JSON →A collection of MCP servers for Electronic Design Automation (EDA) workflows, including tools for die yield calculation and Verilog/SystemVerilog analysis.
Tools · 38
- yosys_synth Synthesis with multiple output formats
- yosys_analyze Design analysis and statistics
- yosys_show Generate visual circuit diagrams
- verilator_compile Compile designs to C++
- verilator_simulate Run simulations with auto-testbench
- verilator_testbenchgenerator Intelligent testbench creation
- verilator_naturallanguage Natural language queries
- verible_lint Style checking and fixes
- verible_format Code formatting
- verible_syntax AST analysis
- verible_analyze Design analysis
- verible_natural_language Natural language queries
- gtkwave_open Open waveforms with configurations
- gtkwave_convert Convert between formats
- gtkwave_extract_signals Extract signal hierarchies
- gtkwave_analyze_timing Timing measurements
- gtkwave_capture_screenshot Generate waveform images
- klayout_layout_info Analyze layout files
- klayout_convert_layout Format conversion
- klayout_run_drc Design rule checking
- klayout_extract_layers Layer extraction
- klayout_execute_script Custom scripting
- klayout_natural_language Natural language queries
- calculate_die_per_wafer Calculate die yield
- validate_parameters Validate input parameters
- get_standard_wafer_sizes Get wafer standards
- find_ip_vendors Search IP core vendors
- find_asic_services Find ASIC services
- get_price_estimation Estimate costs
- compare_vendors Compare multiple vendors
- natural_language_query Natural language interface
- openlane_run_flow Complete RTL to GDSII flow
- openlane_run_synthesis Logic synthesis
- openlane_run_floorplan Floorplanning and I/O placement
- openlane_run_placement Standard cell placement
- openlane_run_cts Clock tree synthesis
- openlane_run_routing Global and detailed routing
- openlane_natural_language Natural language interface
Links
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