SystemRDL Compiler

1.32.2 · active · verified Mon Apr 13

The systemrdl-compiler project implements a generic compiler front-end for Accellera's SystemRDL 2.0 register description language. It provides an elaborated register model that is easy to traverse and query, facilitating the creation of custom register space view generators. The project is actively maintained with frequent minor releases addressing bugs and adding features.

Warnings

Install

Imports

Quickstart

This quickstart demonstrates how to compile a simple SystemRDL string, elaborate it into a register model, and then traverse the resulting `RootNode` to inspect components like registers and fields. The `RDLCompiler` is the entry point, `compile_string` parses the RDL, and `elaborate` creates the hierarchical `RootNode` representation. The `descendants()` and `find_by_path()` methods are shown for model traversal and access.

from systemrdl import RDLCompiler
from systemrdl.node import RootNode, Node

# Create a dummy RDL file content
rdl_content = """
addrmap my_block {
    reg {
        field { sw=rw; } my_field[31:0] = 0;
    } my_register @0x0;
};
"""

# 1. Instantiate the compiler
compiler = RDLCompiler()

# 2. Compile the RDL source
try:
    compiler.compile_string(rdl_content, "dummy.rdl")
except Exception as e:
    print(f"Compilation failed: {e}")
    exit(1)

# 3. Elaborate the design
try:
    # 'my_block' is the top-level addrmap definition name
    root = compiler.elaborate(top_def_name="my_block")
except Exception as e:
    print(f"Elaboration failed: {e}")
    exit(1)

# 4. Traverse the elaborated model
print("Elaborated RDL Model:")
for node in root.descendants(): # Use descendants for recursive traversal
    indent = "  " * node.depth
    print(f"{indent}- {node.get_path()} (Type: {node.type_name})")

# Example: Access a specific register node
reg_node = root.find_by_path("my_block.my_register")
if reg_node:
    print(f"Found register: {reg_node.inst_name} at address {hex(reg_node.addr_offset)}")
    for field in reg_node.fields():
        print(f"  Field: {field.inst_name}, Bits: [{field.msb}:{field.lsb}]")

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