{"id":10173,"library":"pyverilog","title":"Pyverilog","description":"Pyverilog is a Python-based Hardware Design Processing Toolkit for Verilog HDL, providing a parser, dataflow analyzer, controlflow analyzer, and code generator. It allows users to parse Verilog code into an Abstract Syntax Tree (AST), analyze its structure, and extract design information. The current version is 1.3.0, and releases occur periodically, typically every few months, addressing bugs and adding new features.","status":"active","version":"1.3.0","language":"en","source_language":"en","source_url":"https://github.com/PyHDI/Pyverilog","tags":["EDA","Verilog","HDL","parser","AST","dataflow"],"install":[{"cmd":"pip install pyverilog ply","lang":"bash","label":"Install Pyverilog and its required dependency"}],"dependencies":[{"reason":"Required for parsing Verilog. As of v1.3.0, it is no longer bundled and must be installed separately.","package":"ply","optional":false},{"reason":"An external tool often required by Pyverilog's preprocessor for handling Verilog 'include' directives and macros. Must be installed separately on the system PATH.","package":"Icarus Verilog (iverilog)","optional":true}],"imports":[{"symbol":"VerilogParser","correct":"from pyverilog.vparser.parser import VerilogParser"},{"symbol":"vast","correct":"import pyverilog.vparser.ast as vast"},{"symbol":"DataflowAnalyzer","correct":"from pyverilog.dataflow.dataflow import DataflowAnalyzer"},{"symbol":"DotGraph","correct":"from pyverilog.dataflow.graph import DotGraph"}],"quickstart":{"code":"import os\nfrom pyverilog.vparser.parser import VerilogParser\nimport pyverilog.vparser.ast as vast\nfrom pyverilog.dataflow.dataflow import DataflowAnalyzer\nfrom pyverilog.dataflow.graph import DotGraph\n\n# Create a dummy Verilog file for parsing\nverilog_code = \"\"\"\nmodule test_module (input clk, input rst, output reg [7:0] count);\n  always @(posedge clk or posedge rst) begin\n    if (rst) begin\n      count <= 8'h00;\n    end else begin\n      count <= count + 1;\n    end\n  end\nendmodule\n\"\"\"\n\nwith open('example.v', 'w') as f:\n    f.write(verilog_code)\n\n# 1. Parse the Verilog file into an AST\nparser = VerilogParser()\nast = parser.parse(['example.v'])\n\nprint(\"--- Verilog AST --- \")\n# ast.show() # Uncomment to print the full AST\n\n# 2. Perform Dataflow Analysis\nanalyzer = DataflowAnalyzer()\nanalyzer.visit(ast)\n\n# Get dataflow graph and print some nodes\ndfg = analyzer.get_dfg()\nprint(\"\\n--- Dataflow Analysis (some nodes) ---\")\nfor node_id, node in dfg.items():\n    if isinstance(node_id, vast.Port) or isinstance(node_id, vast.Reg):\n        print(f\"Node: {node_id.name}, Type: {type(node_id).__name__}, Defs: {len(node.definitions)}\")\n\n# 3. Generate a DOT graph (requires graphviz and dot command)\n# try:\n#     graph = DotGraph(dfg)\n#     graph.write_dot('dfg.dot')\n#     print(\"\\nDataflow graph written to dfg.dot (requires Graphviz to visualize).\")\n# except Exception as e:\n#     print(f\"\\nCould not generate DOT graph: {e} (Is Graphviz installed?)\")\n\n# Clean up the dummy file\nos.remove('example.v')\n","lang":"python","description":"This quickstart demonstrates how to parse a simple Verilog module into an Abstract Syntax Tree (AST) using `VerilogParser`, and then perform a basic dataflow analysis using `DataflowAnalyzer`. It prints key nodes from the AST and basic information from the dataflow graph. To visualize the dataflow graph as an image, you would also need to install Graphviz and use `DotGraph` to write a '.dot' file which can then be rendered externally."},"warnings":[{"fix":"Explicitly install `ply` using `pip install ply` alongside `pyverilog`.","message":"The `ply` library, a core dependency for Verilog parsing, is no longer bundled with Pyverilog since version 1.3.0. Users upgrading from prior versions will encounter `ModuleNotFoundError` if `ply` is not installed separately.","severity":"breaking","affected_versions":">=1.3.0"},{"fix":"Ensure you are using Python 3.x. Upgrade your Python environment if necessary.","message":"Python 2 support was officially disabled in version 1.1.3. Pyverilog now exclusively supports Python 3.","severity":"breaking","affected_versions":">=1.1.3"},{"fix":"Install Icarus Verilog on your operating system and verify `iverilog` is available in your command-line PATH.","message":"For features like Verilog preprocessor (`-p` or `preprocess=True` in `VerilogParser`) which handle `include` directives or macros, the external tool `Icarus Verilog` (specifically the `iverilog` command) must be installed and accessible in your system's PATH.","severity":"gotcha","affected_versions":"all"},{"fix":"Review any custom preprocessor configurations or `iverilog` commands passed to Pyverilog to ensure they function correctly without `shell=True`. Adjust commands to be direct arguments rather than shell constructs.","message":"In version 1.2.0, the `subprocess.call()` method used within the preprocessor no longer uses `shell=True` for security reasons. This could affect users who relied on specific shell behaviors or complex custom `iverilog` commands that implicitly leveraged shell features.","severity":"breaking","affected_versions":">=1.2.0"}],"env_vars":null,"last_verified":"2026-04-17T00:00:00.000Z","next_check":"2026-07-16T00:00:00.000Z","problems":[{"fix":"Install the `ply` package: `pip install ply`","cause":"Since Pyverilog 1.3.0, the `ply` library is no longer bundled and must be installed as a separate dependency.","error":"ModuleNotFoundError: No module named 'ply'"},{"fix":"Verify your Verilog file for syntax errors. If using preprocessing, ensure `iverilog` is installed and accessible in your PATH, and all `-I` include paths are correctly specified.","cause":"This error typically indicates a syntax error in the Verilog source code, an unsupported Verilog construct, or an issue with the preprocessor (e.g., missing include files, `iverilog` not found).","error":"pyverilog.vparser.parser.ParseError: Cannot parse the source file."},{"fix":"Install `Icarus Verilog` on your system and ensure its executable (`iverilog`) is available in your system's PATH environment variable.","cause":"Pyverilog's preprocessor tries to invoke the `iverilog` command, but it's not found in the system's PATH.","error":"FileNotFoundError: [Errno 2] No such file or directory: 'iverilog'"}]}